Booster circuit

ABSTRACT

Power source voltage is supplied to a boost driver of a booster circuit. The boost driver generates a pulse signal when a boost-starting signal indicative of start of boost is input. A boost capacitor boosts voltage level of an output terminal when the pulse signal is received. A precharge circuit supplies voltage to the output terminal on standby before boosting. A constant-voltage generating circuit supplies constant voltage to the precharge circuit.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a booster circuit used forreading data and such, and more particularly, to a booster circuithaving function for controlling the boosting level within a desiredrange.

[0003] 2. Description of the Related Art

[0004] Conventionally, a booster circuit is used for boosting of a wordline when data stored in a semiconductor storage device is read. Forexample, a conventional booster circuit is described in Japanese PatentApplication Laid-open No. 6-60651. FIG. 1 is a circuit diagram showing aconventional booster circuit described in Japanese Patent ApplicationLaid-open No. 6-60651.

[0005] In the conventional booster circuit, a boost-starting signalATDBST is input to an input terminal of an inverter 505, and a voltageVboost is output from a boost node NDBST. An output terminal of theinverter 505 is connected to an input terminal of an inverter 506, agate of an N-channel MOS transistor 503 and a gate of a P-channel MOStransistor 501. An output terminal of the inverter 506 is connected toone terminal of a boosting capacitor 507 whose capacity is Cb. The otherterminal of the boosting capacitor 507 is connected to the boost nodeNDBST.

[0006] A drain of the N-channel MOS transistor 503 is grounded and asource thereof is connected to a drain of an N-channel MOS transistor504. A source of the N-channel MOS transistor 504 is connected to a gateof a P-channel MOS transistor 502, and the junction point VX thereof isconnected to one of input/output terminals of the P-channel MOStransistor 501.

[0007] Power source voltage VCC is always supplied to a gate of theN-channel MOS transistor 504, and the N-channel MOS transistor 504 isalways in ON state. Further, one of input terminals of the P-channel MOStransistor 502 is connected to the power source voltage VCC, and theother input/output terminal is connected to the boost node NDBST. Theother input/output terminal of the P-channel MOS transistor 501 is alsoconnected to the boost node NDBST.

[0008] In the conventional booster circuit having the above-describedstructure, on standby before boosting, the boost-starting signal ATDBSTis input to the inverter 505 at low level. The level of theboost-starting signal ATDBST is inverted by the inverter 505, and asignal of the level VCC is input to the input terminal of the inverter506, the gate of the N-channel MOS transistor 503 and the gate of theP-channel MOS transistor 501.

[0009] With the above operation, the output signal of the inverter 506is held at low level, and a low level signal is input to the boostingcapacitor 507.

[0010] The N-channel MOS transistor 503 is brought into ON state, andthe boost node NDBST and a gate level (node VX) of the P-channel MOStransistor 502 are held at low level. Therefore, the P-channel MOStransistor 502 assumes ON state. At that time, the P-channel MOStransistor 501 is kept in OFF state. As the P-channel MOS transistor 502is turned ON, the power source voltage level VCC appears in the boostnode NDBST as it is.

[0011] When the boost is started from that state, the boost-startingsignal ATDBST is switched from low level to high level VCC and is inputto the input terminal of the inverter 505.

[0012] With this operation, the output signal of the inverter 505 isinverted from high level VCC to low level, and the output signal of theinverter 506 is inverted from low level to high level VCC.

[0013] Therefore, a signal of high level VCC is applied to one terminalof the capacitor 507, a low level signal is input to the gate of theN-channel MOS transistor 503 and the gate of the P-channel MOStransistor 501. When the signal of high level VCC is applied to the oneterminal of the capacitor 507, the boost node NDBST is boosted from thepower source voltage level VCC to a voltage level shown in the equation(1) by capacitive coupling in the capacitor 507.

Vboost=(1+(Cb/(Cb+Cl)))×VCC  (1)

[0014] When the boost is completed, the input level of theboost-starting signal ATDBST is switched from high level to low level.Therefore, voltage level of each node is returned to level before boostis started. Then, the boost is completed.

[0015] When the above-described conventional booster circuit is used asbooster means for a word line when data is read from a non-volatilesemiconductor storage device, since it is necessary to secure bothreading margin for on-cell and reading margin for off-cell, it isnecessary to control the boost level within a range between the upperlimit target and the lower limit target.

[0016] However, there is a problem that it is extremely difficult togive the highest priority to the achievement of the lower limit target,and to also achieve the upper limit target.

[0017] The reason is that there exist characteristics as dependenceproperties of power source voltage of boost level that the boost levelis proportional to about two times of the power source voltage as shownin the equation (1).

[0018] Further, if the conventional booster circuit is used as boostmeans for a ward line when data is read from a non-volatilesemiconductor storage device, when the voltage level of the word line isexcessively increased, the gate level of memory cell is brought intoboost level, the drain is brought into voltage level of about lV, apseudo weak writing mode is established. Therefore, reading is repeatedand thus, there is a problem that variation is generated in a thresholdvalue of the memory cell by the pseudo weak writing operation.

[0019] The reason is that there exist characteristics as dependenceproperties of power source voltage of boost level that the boost levelis proportional to about two times of the power source voltage asdescribed above.

SUMMARY OF THE INVENTION

[0020] It is an object of the present invention to provide a boostercircuit capable of stably controlling boosting electric potentialwithout depending on the power source voltage with respect to the targetboost upper limit even when electric potential greater than the powersource voltage is boosted.

[0021] According to one aspect of the present invention, a boostercircuit includes an output terminal and a boost driver to which powersource voltage is supplied. The boost driver generates a pulse signalwhen a boost-starting signal indicative of start of boost is input. Thebooster circuit further includes a boost capacitor which boosts voltagelevel of said output terminal when the pulse signal is received, aprecharge circuit which supplies voltage to the output terminal onstandby before boosting, and a constant-voltage generating circuit whichsupplies constant voltage to the precharge circuit.

[0022] According to another aspect of the present invention, a boostercircuit includes an output terminal and a boost driver which generates apulse signal when a boost-starting signal indicative of start of boostis input. The booster circuit further includes a boost capacitor whichboosts voltage level of said output terminal when the pulse signal isreceived, a precharge circuit to which power source voltage is supplied,and a constant-voltage generating circuit which supplies constantvoltage to the boost driver. The precharge circuit supplies voltage tothe output terminal on standby before boosting.

[0023] According to a possible feature of the present invention, abooster circuit includes an output terminal and a boost driver whichgenerates a pulse signal when a boost-starting signal indicative ofstart of boost is input. The booster circuit further includes a boostcapacitor which boosts voltage level of the output terminal when thepulse signal is received, a precharge circuit which supplies voltage tothe output terminal on standby before boosting, and a constant-voltagegenerating circuit which supplies constant voltage to the boost driverand the precharge circuit.

[0024] According to the present invention, at least one of the prechargelevel on standby before boosting and the amplitude level of the boostpulse may be controlled by the constant voltage generated from theconstant-voltage generating circuit. Therefore, since at least one ofthem may be a level which does not rely on the power source voltage, itis possible to easily achieve the upper limit target even if thepriority is given to the lower limit target of the boost level.

[0025] As a result, if the present invention is adapted to boost avoltage level of a word line when data is read from a non-volatilesemiconductor storage device, it is possible to prevent the readingerror due to boost of the voltage level of the word line. Similarly, itis possible to prevent the pseudo weak writing state due to the boost ofthe voltage level of the word line.

BRIEF DESCRIPTION OF THE DRAWINGS

[0026]FIG. 1 is a circuit diagram showing a conventional booster circuitdescribed in Japanese Patent Application Laid-open No. 6-60651;

[0027]FIG. 2 is a block diagram showing a booster circuit of a firstembodiment of the present invention;

[0028]FIG. 3 is a circuit diagram showing the structure of a prechargecircuit 105;

[0029]FIG. 4 is a circuit diagram showing the structure of a boostdriver 102;

[0030]FIG. 5 is a block diagram showing a booster circuit of a secondembodiment of the present invention;

[0031]FIG. 6 is a circuit diagram showing the structure of a prechargecircuit 105 a; and

[0032]FIG. 7 is a circuit diagram showing the structure of a boostdriver 102 a.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0033] Booster circuits of embodiments of the present invention will beexplained concretely with reference to the accompanying drawings below.FIG. 2 is a block diagram showing a booster circuit of a firstembodiment of the present invention.

[0034] In the booster circuit of the first embodiment, a boost-startingsignal ATDBST is input to an input terminal of an inverter 101, and avoltage Vboost is output from a boost node NDBST (high voltage outputterminal). An input terminal of a boost driver 102 is connected to anoutput terminal of the inverter 101. One terminal of a boost capacitor103 is connected to an output terminal of the boost driver 102. A boostpulse is generated from the boost driver 102 to the boost capacitor 103.The boost node NDBST is connected to the other terminal of the boostcapacitor 103. The boost node NDBST is connected to a high voltageoutput terminal (Vboost), and the high voltage output terminal isboosted by the boost capacitor 103 which received the boost pulse. Thecapacity value of the boost capacitor 103 is Cb.

[0035] There is preferably provided a precharge circuit 105 connected tothe high voltage output terminal for supplying voltage to the highvoltage output terminal (Vboost) on standby before boosting. A constantvoltage Vconst is input to the precharge circuit 105 as power source. Anoutput terminal of the precharge circuit 105 is connected to the boostnode NDBST.

[0036] Further, a boost load capacitor 106 may be connected to the boostnode NDBST. The capacity value of the boost load capacitor 106 is Cl.

[0037] The booster circuit is preferably provided with aconstant-voltage generating circuit 104 for supplying the constantvoltage to the precharge circuit 105. The power source voltage VCC issupplied to the constant-voltage generating circuit 104, and theconstant voltage Vconst is output from an output terminal of theconstant-voltage generating circuit 104.

[0038] Next, the precharge circuit 105 used for the booster circuit ofthe first embodiment will be explained. FIG. 3 is a circuit diagramshowing the structure of the precharge circuit 105.

[0039] The precharge circuit 105 can be provided with an inverter 206having an input terminal to which the boost-starting signal ATDBST isinput. An input terminal of an inverter 207 and a gate terminal of anN-channel MOS transistor 204 are connected to an output terminal of theinverter 206. A gate terminal of an N-channel MOS transistor 205 isconnected to an output terminal of the inverter 207.

[0040] A source terminal of the N-channel MOS transistor 204 isgrounded. A drain terminal of a P-channel MOS transistor 201, a gateterminal of a P-channel MOS transistor 202 and a gate terminal of aP-channel MOS transistor 203 are connected to a drain terminal of theN-channel MOS transistor 204.

[0041] A source terminal of the N-channel MOS transistor 205 isconnected to a ground potential. A drain terminal of the P-channel MOStransistor 202 and a gate terminal of the P-channel MOS transistor 201are connected to a drain terminal of the N-channel MOS transistor 205.

[0042] A source terminal of the P-channel MOS transistor 203 isconnected to the constant voltage Vconst, and a drain terminal of theP-channel MOS transistor 203 is connected to the boost node NDBST.

[0043] The boost node NDBST is connected to the source terminals of theP-channel MOS transistors 201 and 202.

[0044] Next, the boost driver 102 used for the booster circuit of thefirst embodiment will be explained. FIG. 4 is a circuit diagram showingthe structure of the boost driver 102.

[0045] The boost driver 102 can be provided with a P-channel MOStransistor 301 having a gate terminal to which an inverted signal BSTINof the boost-starting signal is input. A source terminal of theP-channel MOS transistor 301 is connected to the power source voltageVCC, and a drain terminal of the P-channel MOS transistor 301 isconnected to a boost pulse generating node BOOST.

[0046] The boost driver 102 may be also provided with an N-channel MOStransistor 302 having a gate terminal to which an inverted signal BSTINof the boost-starting signal is input. A source terminal of theN-channel MOS transistor 302 is connected to a ground potential, and adrain terminal of the N-channel MOS transistor 302 is connected to theboost pulse generating node BOOST.

[0047] The operation of the booster circuit of the first embodimentstructured as described above will be explained next.

[0048] On standby before boosting, the boost-starting signal ATDBST isinput to the inverter 101 at low level. The level of the boost-startingsignal ATDBST is inverted by the inverter 101 and a signal of high levelVCC is input to the input terminal of the boost driver 102.

[0049] Thus, the output signal of the boost driver 102 is kept at lowlevel, and the low level signal is input to one of the terminals of theboost capacitor 103. At that time, the voltage Vconst supplied from theconstant-voltage generating circuit 104 appears in the boost node NDBSTas it is through the precharge circuit 105, and electric charge isstored in the boost capacitor 103 and the boost load capacitor 106.

[0050] When the boost is started from that state, the boost-startingsignal ATDBST is switched from low level to high level VCC and is inputto the input terminal of the inverter 101.

[0051] Thus, the output signal of the inverter 101 is inverted from highlevel vcc to low level, and the output signal of the boost driver 102 isinverted from low level to high level VCC.

[0052] Therefore, a signal of high level VCC is applied to one terminalof the boost capacitor 103. When high level VCC signal is applied to oneterminal of the boost capacitor 103, the boost node NDBST is boostedfrom the precharge level Vconst to a voltage level shown in the equation(2) by capacitive coupling in the boost capacitor 103.

Vboost=Vconst+(Cb/(Cb+Cl))×VCC  (2)

[0053] In the equation (2), Vboost is voltage which is output from thehigh voltage output terminal, Vconst is constant voltage which is outputfrom the constant-voltage generating circuit 104, Cb is a capacity valueof the boost capacitor 103, Cl is a capacity value of the boost loadcapacitor 106, and VCC is power source voltage supplied to theconstant-voltage generating circuit 104.

[0054] When the boost is completed, the input level of theboost-starting signal ATDBST is switched from high level to low level.Therefore, voltage level of each node is returned to level before boostis started. Then, the boost is completed.

[0055] As described above, according to the first embodiment, since theprecharge level on standby before boosting is constant voltage whichdoes not rely on the power source voltage, it is easy to control theboost level to the upper limit.

[0056] Next, a second embodiment of the present invention will beexplained. FIG. 5 is a block diagram showing a booster circuit of thesecond embodiment of the invention.

[0057] In the booster Circuit of the second embodiment, a boost-startingsignal ATDBST is input to an input terminal of an inverter 101, and avoltage Vboost is output from a boost node NDBST (high voltage outputterminal). An input terminal of a boost driver 102 a is preferablyconnected to an output terminal of the inverter 101. One terminal of aboost capacitor 103 is connected to an output terminal of the boostdriver 102 a. A boost pulse is generated from the boost driver 102 a tothe boost capacitor 103. The boost node NDBST is connected to the otherterminal of the boost capacitor 103. The boost node NDBST is connectedto a high voltage output terminal (Vboost), and the high voltage outputterminal is boosted by the boost capacitor 103 which received the boostpulse. The capacity value of the boost capacitor 103 is Cb.

[0058] There may be provided a precharge circuit 105 a connected to thehigh voltage output terminal for supplying voltage to the high voltageoutput terminal (Vboost) on standby before boosting. A power sourcevoltage VCC is input to the precharge circuit 105 a as power source. Anoutput terminal of the precharge circuit 105 a is connected to the boostnode NDBST.

[0059] Further, a boost load capacitor 106 is connected to the boostnode NDBST. The capacity value of the boost load capacitor 106 is Cl.

[0060] The booster circuit is preferably provided with aconstant-voltage generating circuit 104 for supplying the constantvoltage Vconst to the boost driver 102 a. The power source voltage VCCis supplied to the constant-voltage generating circuit 104, and theconstant voltage Vconst is output from an output terminal of theconstant-voltage generating circuit 104.

[0061] Next, the precharge circuit 105 a and the boost driver 102 a usedfor the booster circuit of the second embodiment will be explained. FIG.6 is a circuit diagram showing the structure of the precharge circuit105 a and FIG. 7 is a circuit diagram showing the structure of the boostdriver 102 a. In the precharge circuit 105 a shown in FIG. 6 or theboost driver 102 a shown in FIG. 7, elements similar to those of theprecharge circuit 105 or the boost driver 102 shown in FIG. 3 or 4 aredesignated by the same reference numerals, and their detaileddescription will be omitted.

[0062] As shown in FIG. 6, the precharge circuit 105 a used in thesecond embodiment is preferably provided with a P-channel MOS transistor203 a having a source terminal connected to the power source voltageVCC, instead of the transistor 203 having the source terminal connectedto the constant voltage Vconst.

[0063] Further, as shown in FIG. 7, the booster circuit 102 a used inthe second embodiment is preferably provided with a P-channel MOStransistor 301 a having a source terminal connected to the constantvoltage Vconst, instead of the transistor 301 having the source terminalconnected to the power source voltage VCC.

[0064] The operation of the booster circuit of the second embodimentstructured as described above will be explained.

[0065] On standby before boosting, the boost-starting signal ATDBST isinput to the inverter 101 at low level. The level of the boost-startingsignal ATDBST is inverted by the inverter 101 and a signal of high levelVCC is input to the input terminal of the boost driver 102 a.

[0066] Thus, the output signal of the boost driver 102 a is kept at lowlevel, and the low level signal is input to one of the terminals of theboost capacitor 103. At that time, the power source voltage VCC appearsin the boost node NDBST as it is through the precharge circuit 105 a,and electric charge is stored in the boost capacitor 103 and the boostload capacitor 106.

[0067] When the boost is started from that state, the boost-startingsignal ATDBST is switched from low level to high level VCC and is inputto the input terminal of the inverter 101.

[0068] Thus, the output signal of the inverter 101 is inverted from highlevel VCC to low level, and the output signal of the boost driver 102 ais inverted from low level to high level Vconst.

[0069] Therefore, a signal of high level Vconst is applied to oneterminal of the boost capacitor 103. When a high level signal Vconst isapplied to one terminal of the boost capacitor 103, the boost node NDBSTis boosted from the precharge level VCC to a voltage level shown in theequation (3) by capacitive coupling in the boost capacitor 103.

Vboost=VCC+(Cb/(Cb+Cl))×Vconst  (3)

[0070] In the equation (3), Vboost is voltage which is output from thehigh voltage output terminal, Vconst is constant voltage which is outputfrom the constant-voltage generating circuit 104, Cb is a capacity valueof the boost capacitor 103, Cl is a capacity value of the boost loadcapacitor 106, and VCC is power source voltage supplied to theconstant-voltage generating circuit 104.

[0071] When the boost is completed, the input of the boost-startingsignal ATDBST is switched from high level to low level. Therefore,voltage level of each node is returned to level before boost is started.Then, the boost is completed.

[0072] As described above, according to the second embodiment, sinceamplitude level of the boost pulse is constant voltage which does notrely on the power source voltage, it is easy to control the boost levelto the upper limit.

[0073] Although the constant voltage is supplied from theconstant-voltage generating circuit 104 to the precharge circuit 105 inthe first embodiment, and the constant voltage is supplied from theconstant-voltage generating circuit 104 to the booster circuit 102 a inthe second embodiment, the present invention should not be limited tosuch structures.

[0074] For example, the constant voltage may be supplied to both theprecharge circuit and the boost driver from the constant-voltagegenerating circuit. In this case, the precharge circuit is preferablystructured as shown in FIG. 3, and the constant voltage is supplied fromthe precharge circuit to the high voltage output terminal (Vboost) onstandby before boosting. The boost driver is preferably structured asshown in FIG. 7, and the boost pulse is generated from the boost driverto the boost capacitor. The high voltage output terminal is boosted bythe boost capacitor which received the boost pulse. In this case, eachof the precharge level on standby before boosting and the amplitudelevel of the boost pulse is constant voltage which does not rely on thepower source voltage.

What is claimed is:
 1. A booster circuit, comprising: an outputterminal; a boost driver to which power source voltage is supplied, saidboost driver generating a pulse signal when a boost-starting signalindicative of start of boost is input; a boost capacitor which boostsvoltage level of said output terminal when said pulse signal isreceived; a precharge circuit which supplies voltage to said outputterminal on standby before boosting; and a constant-voltage generatingcircuit which supplies constant voltage to said precharge circuit.
 2. Abooster circuit, comprising: an output terminal; a boost driver whichgenerates a pulse signal when a boost-starting signal indicative ofstart of boost is input; a boost capacitor which boosts voltage level ofsaid output terminal when said pulse signal is received; a prechargecircuit to which power source voltage is supplied, said prechargecircuit supplying voltage to said output terminal on standby beforeboosting; and a constant-voltage generating circuit which suppliesconstant voltage to said boost driver.
 3. A booster circuit, comprising:an output terminal; a boost driver which generates a pulse signal when aboost-starting signal indicative of start of boost is input; a boostcapacitor which boosts voltage level of said output terminal when saidpulse signal is received; a precharge circuit which supplies voltage tosaid output terminal on standby before boosting; and a constant-voltagegenerating circuit which supplies constant voltage to said boost driverand said precharge circuit.
 4. A booster circuit according to claim 1 ,wherein said precharge circuit comprises: a field-effect transistorwhose source is connected to said constant-voltage generating circuitand whose drain is connected to said output terminal; and a controlcircuit which controls electric potential of a gate of said field-effecttransistor in association with said boost-starting signal.
 5. A boostercircuit according to claim 1 , wherein said boost driver comprises: afirst field-effect transistor whose gate inputs an inverted signal ofsaid boost-starting signal, said power source voltage being supplied toa source of said first field-effect transistor; and a secondfield-effect transistor whose source is grounded and whose drain isconnected to a drain of said first filed-effect transistor, a gate ofsaid second field-effect transistor inputting an inverted signal of saidboost-starting signal, and a conductive type of a channel of said secondfield-effect transistor being different from that of said firstfield-effect transistor.
 6. A booster circuit according to claim 2 ,wherein said precharge circuit comprises: a field-effect transistorwhose drain is connected to said output terminal, said power sourcevoltage being supplied to a source of said field-effect transistor; anda control circuit which controls electric potential of a gate of saidfield-effect transistor in association with said boost-starting signal.7. A booster circuit according to claim 2 , wherein said boost drivercomprises: a first field-effect transistor whose source is connected tosaid constant-voltage generating circuit, a gate of said firstfield-effect transistor inputting an inverted signal of saidboost-starting signal; and a second field-effect transistor whose sourceis grounded and whose drain is connected to a drain of said firstfiled-effect transistor, a gate of said second field-effect transistorinputting an inverted signal of said boost-starting signal, and aconductive type of a channel of said second field-effect transistorbeing different from that of said first field-effect transistor.
 8. Abooster circuit according to claim 3 , wherein said precharge circuitcomprises: a first field-effect transistor whose source is connected tosaid constant-voltage generating circuit and whose drain is connected tosaid output terminal; and a control circuit which controls electricpotential of a gate of said first field-effect transistor in associationwith said boost-starting signal; and said boost driver comprises: asecond field-effect transistor whose source is connected to saidconstant-voltage generating circuit, a gate of said second field-effecttransistor inputting an inverted signal of said boost-starting signal;and a third field-effect transistor whose source is grounded and whosedrain is connected to a drain of said second filed-effect transistor, agate of said third field-effect transistor inputting an inverted signalof said boost-starting signal, and a conductive type of a channel ofsaid third field-effect transistor being different from that of saidsecond field-effect transistor.